An indigenous IP portfolio, on our own RISC-V

64-bit, Linux-capable RISC-V application cores.

32-bit real-time control and DSP cores.

Lockstep safety cores, ISO 26262 oriented.

One YAML-driven VIP that verifies the RISC-V family.

Systolic-array INT8 inference engine.

Convolution accelerator with a PE array.

Programmable graphics and compute.

Die-to-die chiplet link, FDI and RDI.

Gen1 to Gen5 controller, TL, DL and PL.

SuperSpeed xHCI host controller.

HBM2 to HBM3E multi-channel controller.

DDR4/5 and LPDDR4/5 controller, DFI.

Embedded DisplayPort, PSR and DSC.

Camera interface controller, D-PHY.

Raw to YUV image pipeline.

Functional-safety link, ISO 26262 E2E.