A UCIe 1.1 compliant die-to-die link controller that sits between a chiplet protocol layer and the physical layer. It exposes the flit-aware FDI interface on the protocol side and the raw RDI interface on the PHY side, moves 512-bit mainband flits with CRC-32 protection and a retry replay buffer, runs the full LTSSM link bring-up over a sideband channel, and drives a 16-lane standard package module through an AIB or XSR PHY.
| Category | High-speed interface, UCIe die-to-die link controller |
|---|---|
| Standard | UCIe 1.1 compliant die-to-die adapter |
| Layer interfaces | FDI (flit-aware) on protocol side, RDI (raw) on PHY side |
| Mainband flit | 512-bit flit, 480-bit payload plus 32-bit CRC field |
| Error protection | CRC-32, IEEE 802.3 polynomial 0x04C11DB7, inverted output |
| Retry | Replay buffer depth 16, up to 3 retries, timeout driven |
| Link training | LTSSM: Reset, SBINIT, MBINIT, MBTRAIN, LinkInit, Active, Retrain, L1, L2 |
| Sideband | 128-bit message channel: init, param, train, MBINIT, PM, error, lane repair |
| Protocol modes | Streaming, raw flit, CXL 68B, CXL 256B, PCIe |
| Adapters | AXI4, CXL Type 3, TileLink bridges |
| Module and PHY | 16-lane standard module, 32-bit lanes, AIB and XSR PHY wrappers |
| Power management | Negotiated L1 and L2 low-power entry, lane repair |
| Verification | UVM VIP, compliance checker, reference model, scoreboard, functional coverage |
| Ownership | WIOWIZ IP and WIOWIZ VIP |
Full flit-aware FDI protocol interface and raw RDI PHY interface with valid, irdy and trdy handshakes.
Framed flits carry a 480-bit payload with a 32-bit CRC field appended on the wire.
IEEE 802.3 CRC-32 detects flit errors, a replay buffer retries failed flits up to three times.
Hardware state machine walks reset, sideband init, MBINIT, mainband train and active with L1/L2 power states.
A 128-bit sideband handles parameter exchange, power management, error report and lane repair.
AXI4, CXL Type 3 and TileLink bridges map on-die traffic onto the UCIe flit stream.
