WIOWIZ designs its RISC-V cores in-house. They sit at the centre of the WIOWIZ SoC templates and act as the control plane for the accelerators, protocol and memory IP around them. The families range from a small microcontroller core to a 64-bit application processor that runs an operating system, a lockstep functional-safety island, and an AI tensor extension. Everything in the matrix below is drawn from the current engineering reports, with honest status where evidence is still being built.
The stack read from the bottom up: ISA and RTL, the compiler toolchain, firmware, and the operating system layer. Status is stated per core class, honestly, and where a layer is not an applicable target for a class it is marked N/A rather than left blank.
| Stack layer | Application-class | Microcontroller | Safety |
|---|---|---|---|
| ISA and RTLarchitectural verification | ✓ VerifiedRISCOF ISA suites pass; broad benchmark validation | ✓ VerifiedRISCOF suites pass with coverage closure | ✓ VerifiedValid-contract RISCOF plus formal assets |
| GCC / LLVM toolchaincompile, link, runtime | → In progressToolchain audit for the class still open | ✓ VerifiedCodegen, LTO, LLD and binutils accepted | ✓ VerifiedFull toolchain acceptance |
| OpenSBI firmwaresupervisor boot interface | ◑ PartialReal OpenSBI v1.6 reaches Linux | · N/ABare-metal and RTOS target | · N/ABare-metal and RTOS target |
| Linuxkernel bring-up | ◑ PartialLinux 6.12 early boot on FPGA; userspace init blocked by a tracked core defect | · N/A | · N/A |
| FreeRTOSreal-time kernel | · N/ALinux is the OS target for this class | ✓ VerifiedKernel demonstrated in the software tree | ✓ VerifiedKernel evidence retained |
RV64GC with Sv39 virtual memory, hardware page-table walk and PMP. Boots OpenSBI and Linux, and is the family's FPGA bring-up target.
RV32IMC through IMACF, single- and quad-core with FPU, caches, coherence and CLINT/ACLINT. Runs bare-metal firmware and FreeRTOS.
RV32IMCF with dual-rail lockstep, ECC memories, BIST, safe-state FSM and formal prove-and-cover on the safety mechanisms.
An INT8 MAC array wired in as a functional unit through a custom-opcode extension, with a standalone systolic tensor tile as the reference.
| Role | Control plane inside the WIOWIZ SoC templates, and reference targets for the verification and EDA flow |
|---|---|
| Base ISA | RV32IMC, RV32IMACF and RV64GC, with optional INT8 tensor and RVV 1.0 vector extensions |
| Verification | Directed ISA suites, RISCOF compliance runs, firmware and RTOS boot, formal proofs on the safety island, coverage closure on the microcontroller core |
| Bring-up | Application-class core synthesised to FPGA; OpenSBI and early Linux reached on-board, userspace boot in progress |
| Backend | Sky130 synthesis and place-and-route scripts prepared with clean static timing on the microcontroller core; full physical sign-off in progress |
| Boundaries | Not silicon-proven, not compliance-certified; maturity is stated per capability in the matrix above |
