A synthesizable PCI Express controller that implements the complete layered stack. The Transaction Layer builds and parses TLPs, the Data Link Layer handles ACK and NAK replay and credit based flow control, and the Physical Layer interface drives an LTSSM over PIPE. A scatter-gather DMA engine and address translation move data across AXI4, while a config space carries the Type 0 and Type 1 headers with MSI, MSI-X and power management.
| Category | High-speed interface, PCI Express controller |
|---|---|
| Protocol layers | Transaction Layer, Data Link Layer, Physical Layer interface |
| Generations | Gen1 to Gen5 (2.5, 5.0, 8.0, 16.0 and 32.0 GT/s), configurable max speed |
| Link width | x1 to x16, configurable lane count |
| Encoding | 8b/10b (Gen1 and Gen2), 128b/130b with scrambler (Gen3 and above) |
| Device types | Endpoint, Root Complex, Switch |
| Config space | 4 KB space, Type 0 and Type 1 headers, MSI, MSI-X, Power Management, AER |
| DMA | Scatter-gather DMA engine, read and write channels, linked-list and ring modes, per-descriptor interrupt |
| Address translation | ATU with inbound and outbound regions, first-match priority, bypass mode |
| Data Link services | LCRC-32, DLLP CRC-16, ACK and NAK replay buffer, credit based flow control |
| Physical Layer | PIPE interface, LTSSM, training and ordered sets, scrambler |
| System interface | AXI4 master and slave, APB register interface |
| Verification | UVM VIP, Root Complex and Endpoint models, scoreboard, protocol checkers, functional coverage |
| Ownership | WIOWIZ IP and WIOWIZ VIP |
Transaction, Data Link and Physical layers implemented as clean, decoupled blocks.
Configurable maximum speed from 2.5 GT/s to 32 GT/s across x1 to x16 lanes.
Independent read and write channels with linked-list and ring descriptors over AXI4.
Type 0 and Type 1 headers with MSI, MSI-X, power management and AER.
ACK and NAK replay, LCRC and DLLP CRC, and credit based flow control.
Root Complex and Endpoint models, scoreboard and coverage, WIOWIZ IP and VIP.
