The VIP is independent of the processor RTL. A small core-specific adapter maps a core's retirement interface to a normalized interface, and the architectural monitors, assertions, coverage and reference-model bridges consume only that. One VIP covers many cores by changing a profile.
Retired instructions are checked against a reference model over the normalized retirement interface.
Privilege transitions, CSR behaviour, traps and interrupts are monitored and covered.
Physical memory protection and Sv39/Sv48 address translation are covered through dedicated monitors.
Assertions hold over time on the normalized retirement and memory interfaces.
Features a profile does not implement are excluded from coverage and checking, so scope matches the core.
Architecturally visible defects are injected and each checker is proven to catch its own class of fault.
A single YAML/JSON profile selects the ISA, privilege model, MMU mode, platform CSRs such as mtime and mtimecmp, and the feature exclusions. The same VIP retargets across the application, MCU and safety profiles by loading a different file, with no change to the checkers or coverage. The excerpt below is a real platform configuration: implemented CSRs carry their addresses, and unimplemented features are flagged so they are held out of scope.
| Interface | Normalized retirement and memory interface, driven through a small core-specific adapter |
|---|---|
| Coverage | Architectural, privilege, CSR, trap, interrupt, PMP and virtual memory |
| Checks | Temporal assertions on retirement and memory, plus mutation must-bite proof of the checkers |
| Profiles | Application (RV64IMAC / Sv39), MCU (RV32IMACF), safety (RV32IMCF), selected by class of core |
| Tooling | Portable interface and assertion layer for lightweight checks; full covergroups and UVM on native FSimX |
| Design level | RTL, technology independent |
