// THE PLATFORM
One native DAG, from spec to evidence-sealed GDSII
The WIOWIZ CLI runs the full silicon flow as a single native pipeline, every stage a WIOWIZ engine, every result sealed with evidence.
WIOWIZ CLI ORCHESTRATOR
The orchestrator topologically sorts the stage DAG, resolves @stage.artifact handoffs, fans out ready stages, applies verdict gates and reuses byte-stable results. The adapter registry binds each logical stage to a native WIOWIZ engine.
wz flow run ← flow_steps.yaml
input entering the orchestrator
Every handoff passes through the central spine. For each stage the orchestrator feeds input ▶ and the stage ◀ emits its artifact and evidence capsule back. Engines never call each other.
PHASE 1 INPUT, INTENT & PRE-SYNTHESIS PROOF
01
Project inputs
RTL, TB, PDK
SDC, UPF, LEF, Liberty
◀ feeds input
artifact + capsule ▶
feeds input ▶
◀ artifact + capsule
02
Setup & guardrails
wz setup, doctor
native engines only
03
RTL simulation
FSimX
SoC, chip, VCD, GLS-ready
◀ feeds input
artifact + capsule ▶
feeds input ▶
◀ artifact + capsule
04
CDC & formal
Truti, vWIZ-Formal
structural audit, properties
05
Low-power intent
vWIZ-LP
UPF lint, intent signoff
◀ feeds input
artifact + capsule ▶
feeds input ▶
◀ artifact + capsule
06
Synthesis
APARA
RTL → gate netlist
PHASE 2 NETLIST PROOF & RTL → DEF IMPLEMENTATION
07
Netlist equivalence
vWIZ-LEC
RTL ≡ mapped netlist
◀ feeds input
artifact + capsule ▶
feeds input ▶
◀ artifact + capsule
08
Structural proof
vWIZ-NDB
synth GLS, waveform eq
09
DFT insertion
vWIZ-DFT
scan, ATPG, BIST, JTAG
◀ feeds input
artifact + capsule ▶
feeds input ▶
◀ artifact + capsule
10
Pre-layout timing
vWIZ-STA
constraints, WNS/TNS
11
Place & route
APARA Compiler
floorplan, place, CTS, route
◀ feeds input
artifact + capsule ▶
feeds input ▶
◀ artifact + capsule
12
Routed DEF
APARA boundary
physical handoff
PHASE 3 EXTRACTION, SIGNOFF & TAPEOUT
13
GDS stream
vWIZ-GDS
DEF → GDSII
◀ feeds input
artifact + capsule ▶
feeds input ▶
◀ artifact + capsule
14
Physical verify
vWIZ-Signoff
DRC, LVS, extraction
15
Parasitics & timing
vWIZ-PEX, vWIZ-STA
SPEF, SDF, timing GLS
◀ feeds input
artifact + capsule ▶
feeds input ▶
◀ artifact + capsule
16
Signoff fleet
power, PPA, IR, SI
EM, thermal, SPICE
17
Tapeout gate
human approval
all required proofs present
◀ feeds input
verdict + capsule ▶
feeds input ▶
◀ artifact + capsule
18
GDSII + capsule
tape-out ready
hash-pinned chain of custody
evidence-sealed GDSII
hash-pinned chain of custody
Coverage & debug
vWIZ-Coverage, vWIZ-Wave, vWIZ-DTree
Prototype & emulation
vWIZ-Prototyping, vWIZ-VHE
Evidence contract
command, env, I/O SHA-256, metrics, verdict, log on every stage
Honest gating + cache
PASS, CONDITIONAL, INCONCLUSIVE, FAIL → block / continue
the traditional silicon flow, connected by WIOWIZ CLI and evidence at every stage
