A synthesizable eDP source controller that drives the main link over configurable lanes, negotiates and trains the link through the AUX channel, and packetises video into the main stream. It covers the 8b/10b link rates and the UHBR 128b/132b rates, with panel self refresh, display stream compression and forward error correction built in.
| Category | Display and multimedia, Embedded DisplayPort source controller |
|---|---|
| Standards | VESA eDP 1.4b and eDP 1.5, DisplayPort 2.1, DSC 1.2a |
| Main link lanes | 1, 2 or 4 lanes |
| 8b/10b rates | RBR 1.62, HBR 2.70, HBR2 5.40, HBR3 8.10 Gbps per lane |
| UHBR rates | 128b/132b UHBR10 10.0, UHBR13.5 13.5, UHBR20 20.0 Gbps per lane |
| Link training | Clock recovery and channel EQ FSM, TPS1-4, fast link training, rate and lane fallback, LTTPR |
| AUX channel | Manchester-II encoded, 1 MHz symbol rate, HPD detection, backlight and multi-touch over AUX |
| Main stream transport | TU packing, MSA, VB-ID, BS and BE framing, enhanced framing, SDP for VSC, PPS, audio and HDR |
| Coding | 8b/10b and 128b/132b, LFSR scrambler, ASSR, FEC with RS parity, frame CRC-16 |
| Video path | Pixel to link clock FIFO, up to 3840 by 2160, 6 to 16 bits per component |
| Power and features | PSR1 and PSR2, Adaptive Sync and VRR, GTC, MSO 2x1, 2x2 and 4x1 |
| Host interface | APB CSR register bank, AXI4 framebuffer DMA master |
| Verification | UVM VIP, reference model and scoreboard, functional coverage |
| Ownership | WIOWIZ IP and WIOWIZ VIP |
Drives 1, 2 or 4 lanes across the 8b/10b RBR to HBR3 rates and the 128b/132b UHBR rates.
Clock recovery and channel EQ with TPS1-4, fast link training and automatic rate and lane fallback.
Manchester-II AUX at 1 MHz with HPD detection, DPCD access, backlight and multi-touch over AUX.
TU packing with MSA, VB-ID and enhanced framing, plus SDP insertion for VSC, PPS, audio and HDR.
PSR1 full frame and PSR2 selective update cut link activity on static content.
Reference model, scoreboard and coverage, WIOWIZ IP and VIP.
