The WIOWIZ NPU is a systolic-array inference accelerator built around an INT8 multiply-accumulate array with INT32 accumulation and a weight-stationary dataflow. A hardware transformer sequencer walks attention, LayerNorm and feed-forward layers while a host command mailbox dispatches descriptors in order. Weights and activations stay on-chip in banked, double-buffered SRAM so compute and DMA overlap, and an AXI master moves tensors to and from external memory with the host path built on the WIOWIZ PCIe block. The IP ships as a family: arka is the frozen reference, v1 is the IP-sovereign design shipped today, and v2 extends the datapath to mixed INT4, INT8 and FP8 precision with state-space streaming, sparse attention and Mixture-of-Experts routing.
| Category | AI accelerator, Neural Processing Unit |
|---|---|
| Family | Three generations: arka frozen reference, v1 IP-sovereign design shipped today, v2 in specification |
| Compute | Systolic INT8 multiply-accumulate array, weight-stationary dataflow, INT32 accumulation |
| Precision | INT8 activations and weights in v1; mixed INT4, INT8 and FP8 planned for v2 |
| Sequencer | Hardware transformer sequencer, WIOWIZ-authored in v1, walks attention, LayerNorm and feed-forward layers |
| On-chip memory | Banked weight and activation SRAM, double buffered for compute and DMA overlap |
| Command model | Host command mailbox with an in-order descriptor ring |
| Host interface | PCIe host path on the WIOWIZ PCIe block, APB CSR configuration |
| Memory interface | AXI master DMA to external memory |
| Post-processing | Integer LayerNorm with inverse-square-root LUT, activation and GELU LUT, per-channel quantization |
| Reliability | SECDED ECC on the L2 datapath, per-bank parity, watchdog timer, built-in self-test, bank write-protect |
| Sparsity | Structured zero-skip, verified numerically identical to dense compute |
| v2 architecture | State-space (SSM) streaming, sparse attention, Mixture-of-Experts routing, reconfigurable per-layer dataflow |
| Verification | Native FSimX, golden reference model, scoreboard, functional coverage, error-injection runs |
| IP sovereignty | Every RTL line WIOWIZ-authored or referencing a sibling WIOWIZ IP or RISC-V core |
| Ownership | WIOWIZ IP and WIOWIZ VIP |
A weight-stationary INT8 multiply-accumulate array with INT32 accumulation runs dense and batched GEMM.
A hardware sequencer walks attention, LayerNorm and feed-forward layers with no host CPU in the compute loop.
Banked on-chip weight and activation memory lets compute read one buffer while DMA fills the other.
Every line is WIOWIZ-authored or references a sibling WIOWIZ IP or RISC-V core; the host path uses the WIOWIZ PCIe block.
SECDED ECC on the L2 datapath, per-bank parity, watchdog and built-in self-test guard the memory system.
Native FSimX regression, a golden reference model and functional coverage check GEMM, attention, LayerNorm, FFN and sparsity.
