A SuperSpeed USB host controller built on an xHCI register and ring model. Command, transfer, and event rings drive a slot and endpoint manager, the protocol layer handles transaction and data packets, and the link layer runs the LTSSM, header sequencing, credit flow control, and retry down to a PIPE PHY interface. Descriptors and payloads move over an AXI4 master, control is through APB, and the design spans Gen1, Gen2, and Gen2x2 rates.
| Category | High-speed interface, SuperSpeed USB host controller |
|---|---|
| Rates | Gen1 5 Gbps, Gen2 10 Gbps, Gen2x2 20 Gbps (SuperSpeed and SuperSpeedPlus) |
| Host model | xHCI registers, doorbell, command / transfer / event TRB rings |
| Endpoints | Slot and endpoint context manager, control · bulk · interrupt · isochronous, stream support |
| Protocol layer | Transaction packets (ACK, NRDY, ERDY, STATUS, STALL, PING), data packets, ITP, LMP |
| Link layer | LTSSM (Rx.Detect, Polling, U0 to U3, Recovery, Hot Reset, Loopback, Compliance), header sequencing, credit flow control, retry |
| Encoding | 8b/10b for Gen1, 128b/132b for Gen2, LFSR scrambler, CRC32 and CRC16 |
| PHY interface | PIPE 32-bit per port, LFPS, training sequences, Rx detect, power states P0 to P3 |
| System interface | AXI4 64-bit master to memory, APB CSR |
| Verification | UVM VIP, compliance suite, scoreboard, functional coverage |
| Ownership | WIOWIZ IP and WIOWIZ VIP |
Doorbell, command, transfer, and event rings drive the datapath with no host CPU in the loop.
Per-slot endpoint contexts cover control, bulk, interrupt, and isochronous transfers plus streams.
Rx.Detect through Polling, U0 to U3, Recovery, Hot Reset, Loopback, and Compliance states.
Header sequence numbers, credit-based flow control, and retry on LBAD keep the link clean.
8b/10b and 128b/132b encoding with scrambling across 5, 10, and 20 Gbps rates.
Compliance suite, scoreboard, and coverage, WIOWIZ IP and VIP.
