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SOFT IP / HIGH-SPEED INTERFACES / DDR

DDR Memory Controller

DDR4, DDR5, LPDDR4 and LPDDR5 controller with DFI 5.0 PHY interface, WIOWIZ IP and WIOWIZ VIP

One configurable core for DDR4, DDR5, LPDDR4 and LPDDR5

A synthesizable DDR memory controller built around a bank-aware command scheduler. An AXI4 host port feeds a reorder buffer and scheduler that track every bank, resolve page hits and conflicts, and enforce full JEDEC timing, then drive DRAM over a DFI 5.0 PHY interface. Refresh, ZQ calibration, training, and inline SECDED ECC run alongside the datapath.

APB CSR, Configuration and Timing Registers HOST FRONT-END SCHEDULING CORE MEMORY MANAGEMENT AXI4 Host Port64-bit data, 8-bit ID Reorder Buffer16-deep, hazard check Address Mapperrow, bank, col hash Command Scheduler per-bank FSMspage hit, miss, conflict4-pass priority scanJEDEC timing checkeropen, close page policy Bank State Machinesup to 16 banks Refresh and ZQREFab, REFsb, RFM SECDED ECCHsiao 72,64, scrub Training FSM: MRS, write level, eye, VREF DFI 5.0 PHY Interface (command, address, write and read data, 1:1 / 2:1 / 4:1)
Clean architectural view. Real parameters from the WIOWIZ DDR controller RTL.

Specifications

CategoryDDR memory controller with DFI PHY interface
Memory supportDDR4, DDR5, LPDDR4, LPDDR5 (LPDDR4X and LPDDR5X selectable)
TopologyUp to 4 ranks, 4 bank groups, 4 banks per group (16 banks), row up to 18 bits, column 10 bits
Burst and dataBurst length 8, configurable DQ width (16-bit default)
Host interfaceAMBA AXI4 slave, 64-bit data, 32-bit address, 8-bit ID, 8 outstanding reads and 8 writes
ConfigurationAPB CSR, 12-bit address, 32-bit data
PHY interfaceDFI 5.0, 1:1, 2:1 and 4:1 frequency ratios, frequency-change handshake, training interfaces
SchedulingPer-bank state machines, page hit, miss and conflict handling, open and close page policy, 4-pass priority scan, reorder buffer with RAW, WAW and WAR hazard checks, QoS and anti-starvation
Timing enginetRCD, tRP, tRAS, tRC, tFAW, tCCD, tWTR, tRRD (bank-group aware), tRFC and tRFCsb
RefreshPeriodic all-bank, DDR5 per-bank REFsb, DDR5 RFM Rowhammer mitigation, temperature-compensated 2x and 4x, refresh debt, self-refresh
Calibration and trainingZQCL and ZQCS, MRS, write leveling, gate training, read and write eye, CA training, VREF, timeout and retry
Data protectionInline SECDED ECC (Hsiao 72,64), poison injection, background scrub
Power managementPower-down entry and exit FSM, self-refresh, deep power-down
VerificationSVTB and UVM VIP, reference model scoreboard, self-checking tests, functional coverage
OwnershipWIOWIZ IP and WIOWIZ VIP

Key features

Multi-standard core

DDR4, DDR5, LPDDR4 and LPDDR5 from one configurable, synthesizable controller.

DFI 5.0 PHY interface

1:1, 2:1 and 4:1 frequency ratios, frequency-change handshake, and a full write level, gate, eye and VREF training path.

Bank-aware scheduler

Per-bank state machines, page policy and a 4-pass priority scan drive high bus utilization.

DDR5 refresh management

Per-bank REFsb and RFM Rowhammer mitigation with refresh debt and temperature compensation.

Inline SECDED ECC

Hsiao 72,64 correction with poison injection and a background scrub engine.

AXI4 host port

64-bit slave with 8 outstanding reads and writes, reorder buffer, hazard checks and QoS.

Applications

SoC main memoryDatacenter and AI acceleratorsAutomotive and ADASNetworkingHigh-performance computingEdge compute
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