A programmable GPU built from 16 streaming multiprocessors, each running 32-thread warps on a 32-lane FP32 fused multiply-add datapath backed by a 256-register-per-thread file and 64 KB of banked shared memory. A command processor and work distributor dispatch thread blocks, a Greedy-Then-Oldest scheduler issues one warp per cycle, and memory traffic is coalesced onto a WAI crossbar into a 4 MB banked L2 with stride prefetch and a DRAM scheduler.
| Category | Programmable GPU, graphics and compute pipeline |
|---|---|
| Shader cores | 16 streaming multiprocessors (SMs) |
| Threading | 32 threads per warp, 8 warp slots per SM |
| Compute | 32-lane FP32 fused multiply-add per SM, 512 FP32 lanes across the GPU, 4-stage FMA pipeline |
| Integer | Per-lane integer ALU (add, multiply, logic, shift, compare) |
| Register file | 256 registers per thread |
| Shared memory | 64 KB per SM, 32 banks |
| Warp scheduler | Greedy-Then-Oldest, zero-cycle warp switch, one issue per cycle |
| L2 cache | 4 banks, 4 MB total, 8-way, 64-byte lines, per-bank MSHR |
| Memory system | WAI crossbar fabric, address coalescing, stride prefetch, DRAM scheduler with 4 request queues |
| ISA | 64-bit fixed instructions, 32 KB shared instruction memory |
| Host interface | Register and command interface, APB performance counters, WAI to AXI4 and APB4 bridges |
| Software stack | Mesa Gallium driver, LLVM backend, reference assembler and ISA simulator |
| Verification | UVM VIP, golden reference model, scoreboard and functional coverage |
| Ownership | WIOWIZ IP and WIOWIZ VIP |
Sixteen streaming multiprocessors run 32-thread warps on 32-lane FP32 FMA and per-lane integer ALUs.
A Greedy-Then-Oldest scheduler switches warps with zero cycle penalty and issues one warp every cycle.
Each SM has 64 KB of 32-bank shared memory alongside a 256-register-per-thread file.
Per-warp coalescing groups 32 lane addresses by cache line before issuing WAI requests.
A four-bank, eight-way L2 with stride prefetch and a DRAM scheduler feeds the shader array.
A Mesa Gallium driver, LLVM backend, assembler and ISA simulator target the 64-bit ISA.
