A synthesizable MIPI CSI-2 receiver and transmitter. The receiver merges D-PHY data lanes into a byte stream, decodes each packet header with Hamming ECC, checks long-packet payloads with CRC-16, demultiplexes virtual channels, and unpacks RAW, YUV and RGB pixels onto AXI4-Stream. A DMA engine writes frames to memory over AXI4, while configuration and status run over APB.
| Category | Camera interface controller, MIPI CSI-2 receiver and transmitter |
|---|---|
| Standards | MIPI CSI-2 v2.0 and v3.0, MIPI D-PHY v2.5 PPI |
| PHY interface | D-PHY PPI, one byte per lane, up to 8 data lanes |
| Lanes | 1, 2, 4 or 8 D-PHY data lanes, runtime configurable with SoT skew alignment |
| Virtual channels | Up to 16 virtual channels, optional 2-byte DataIDExt for extended VC |
| Packet decode | Header Hamming ECC (1-bit correct, 2-bit detect), CRC-16 CCITT payload check |
| Pixel formats | RAW6/7/8/10/12/14/16/20/24, YUV420 and YUV422 (8 and 10-bit), RGB444/555/565/666/888, embedded 8-bit |
| Host interface | AXI4 master DMA (up to 256-bit), APB CSR |
| Video output | AXI4-Stream, per-VC ports, tuser {VC, DT, SOF, EOF} |
| Status | Per-VC frame and line counters, ECC, CRC and SoT error counters, interrupt controller |
| Verification | UVM VIP, golden-model scoreboard, functional coverage |
| Ownership | WIOWIZ IP and WIOWIZ VIP |
Short and long packet decode with FS, FE, LS, LE sync and word-count payload handling.
Header Hamming ECC corrects single-bit and detects double-bit errors, CRC-16 checks each payload.
Per-VC demux with DataIDExt support for extended virtual channel addressing.
RAW, YUV, RGB and embedded data unpacked to AXI4-Stream, per-VC output ports.
Byte interleaving and SoT skew alignment across 1, 2, 4 or 8 data lanes.
Golden-model scoreboard and coverage, WIOWIZ IP and VIP.
