WIOWIZ AIwiowiz AI
Note: WIOWIZ EDA tools are in-house, not commercial grade. We build them to autonomize the chip design flow.
// IN-HOUSE EDA

An EDA stack we build ourselves

One native flow from RTL to GDSII, implementation, verification and sign-off, each stage a WIOWIZ engine with AI and evidence built in. See the flow on the How It Works page.

STUDIO FSimX StudioDesktop simulation and debug: FSimX engine, vWIZ-Wave and vWIZ-Coverage in one window, downloadable. Open & download →
// IMPLEMENTATION

Implementation

APARARTL→PnR

Native RTL-to-place-and-route implementation engine, synthesis through routing.

 vWIZ-GDSGDS

DEF to GDSII streaming and layout generation.
// VERIFICATION

Verification & Debug

FSimXSIM

RTL and gate-level logic simulation for SoC and chip.

 vWIZ-FormalFV

Formal property and equivalence verification.

 vWIZ-CoverageCOV

Code, functional, assertion and formal coverage closure.

 vWIZ-WaveDEBUG

Waveform viewer and debug.

 TrutiCDC

CDC and RDC structural audit and sign-off.

 vWIZ-LintRTL Lint

Standalone RTL lint with a no-false-clean guarantee.
// SIGNOFF

Timing, Power & Physical Sign-off

vWIZ-STATIMING

Static timing analysis and timing sign-off.

 vWIZ-SignoffPV

DRC, LVS and parasitic-extraction physical sign-off.

 vWIZ-LPPOWER

Low-power and UPF power-intent verification.

 vWIZ-DFTTEST

Design-for-test, ATPG and test closure.

 vWIZ-SPICESPICE

Transistor-level and mixed-signal simulation.
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