FSimX is WIOWIZ's own event-driven Verilog and SystemVerilog simulator, built from scratch in C++20 with full 4-state (0/1/X/Z) value semantics. It compiles, elaborates and simulates synthesizable RTL, UVM testbenches and gate-level netlists at SoC and chip scale, enforcing IEEE 1800-2017 strictly and emitting standard VCD and FST waveforms for debug. Validated against open-source RISC-V cores and Google's OpenTitan silicon root of trust.
Event-driven Verilog/SystemVerilog with 4-state logic, procedural blocks, classes/OOP, fork-join and IEEE 1800-2017 strict conformance.
Structural netlist simulation with SDF timing annotation (IEEE 1497), min/typ/max corners, standard-cell library loading and setup/hold violation checks.
Runs full SoC-level UVM testbenches; validated on OpenTitan IPs including AES with 122K signals, KMAC, SPI, UART, GPIO and RISC-V debug.
IEEE 1364 VCD output plus compressed FST (~13x smaller, GTKWave-native) for waveform inspection and archival debug.
Bundled Accellera UVM 1.2: component hierarchy, phases, sequences, factory, register layer (RAL), scoreboards and analysis ports.
Scripted example and regression suites across Verilog, SystemVerilog, UVM, netlist, SoC IP and OpenTitan, with reproducible version-controlled artifacts.
| Stage | Functional verification, RTL and gate-level logic simulation |
|---|---|
| Languages | Verilog and SystemVerilog (IEEE 1800-2017), Accellera UVM 1.2, Verilog-A Level 1 |
| Value model | 4-state (0/1/X/Z), dual-bit encoding up to 256-bit wide signals with carry-propagating arithmetic |
| Design level | Synthesizable RTL and gate-level netlists, SoC and chip scale |
| Waveforms | VCD (IEEE 1364) and FST compressed output |
| Gate-level timing | SDF annotation (IEEE 1497), min/typ/max corners, setup/hold checks, Liberty cell library loading |
| Power-aware | IEEE 1801 UPF: power domains, isolation, retention, level shifters, power-state tables |
| PDK / technology | Not required for RTL; gate-level simulation uses the technology Verilog cell library. FSimX is a logic simulator, technology independent for RTL. |
| Backend | Interpreter with full debug, plus IR-to-C++ compiled codegen backend |
| Platform | Linux x86_64 (Ubuntu 22.04+, RHEL 8+), CLI-first fsxrun |
