APARA is WIOWIZ's native digital implementation engine. It begins with synthesizable RTL and ends with a routed physical database and a traceable handoff package for downstream timing and physical signoff. Synthesis, floorplan, placement, clock-tree synthesis and routing run as an inspectable chain of transformations rather than a black box: each stage receives immutable inputs from the one before it and emits independently checkable artifacts, so a designer can reproduce or diagnose a single transformation without rerunning the rest of the flow.
Native RTL elaboration and bit-level lowering, technology mapping with per-PDK cell and pin bindings, and fanout-driven drive-strength selection into mapped Verilog with verified Liberty cell interfaces.
Core and die geometry built from real Liberty cell areas, row creation and macro placement, with explicit LEF-bound hard macros and an immutable floorplan-to-placement handoff. Missing macro geometry fails loud.
Force-directed global placement with I/O anchoring, a guarded analytical path, deterministic detailed row refinement and Tetris-style legalization, honouring fences, placement blockages and external LEF geometry.
Clock-tree construction that recognises real mapped flop and buffer cells through reverse technology mapping, producing a clocked DEF for the routing stage.
Global and detail routing to a routed DEF, with track- and layer-assignment solvers and reports on wirelength, RMST comparison, connectivity, layer use and residual design-rule information.
An internal static-timing engine with NLDM interpolation and power estimation guides implementation; net criticality and slack weight timing-driven placement, and independent overlap, boundary, row-legality and HPWL oracles check each result.
| Stage | Digital implementation: synthesis, floorplan, placement, clock-tree synthesis and routing |
|---|---|
| Flow | Six-stage run flow with stop-after and per-stage enablement controls |
| Inputs | Synthesizable RTL, SDC timing constraints, and PDK technology data (LEF, Liberty) |
| Outputs | Mapped netlist, floorplan, placed DEF, CTS DEF, routed/final DEF, net-slack data, reports and a handoff manifest |
| Verdicts | Structured signoff-style gates distinguishing PASS, WARN, FAIL and DATA_UNAVAILABLE |
| PDK / technology | PDK-dependent: uses LEF, Liberty and technology files for the target process |
| Handoff | Auditable package for VWiz-STA, VWiz Signoff and related downstream tools |
| Boundary | Internal timing and physical checks guide implementation; final MCMM STA, PEX, LVS and DRC verdicts remain downstream |
