// EDA · RESEARCH & DEVELOPMENT
The road to full-flow sign-off
Our beta-stage tools already cover simulation, debug, coverage,
formal, CDC, power and SPICE. These backend and sign-off engines
complete the WIOWIZ RTL-to-GDSII vision. They are in research and
development — described here for what they will do, not offered
as released products.
← back to beta-stage EDA tools
Tulya-Equivalence CheckR&D
Logic Equivalence Check
Proves two representations of a design are logically identical, so
transformations along the flow are provably safe.
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RTL vs. synthesized netlist, and netlist vs. netlist after DFT
insertion, ECOs and place-and-route
-
Combinational and sequential equivalence with key-point matching
- Non-equivalence debug down to the failing cone of logic
Static Timing Analysis · pre / post-layout
Vectorless timing sign-off across the operating space, from early
estimates to final extracted timing.
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Setup and hold across process, voltage and temperature corners
- On-chip variation and multi-mode multi-corner analysis
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Pre-layout on estimated parasitics, post-layout on extracted RC
for closure
Kriya DFTR&D
Design-for-Test · scan · ATPG · MBIST
Testability built into the netlist so manufactured silicon can be
screened for defects.
- Scan-chain insertion and reordering
- ATPG for stuck-at and at-speed (transition) faults
- Memory BIST (MBIST) and boundary scan (JTAG)
Chaturang · physical sign-off · four limbs: DRC, LVS, PEX and GDS
Manufacturing sign-off of the final layout, feeding accurate
parasitics back into timing and power closure.
- DEF-to-GDSII streaming and layout generation (chaturang-gds)
- Design-rule checking (chaturang-drc) against the foundry deck
- Layout-versus-schematic (chaturang-lvs) connectivity match
-
Parasitic extraction (chaturang-pex) of RC for accurate back-annotation
