EDA TOOLS / VERIFICATION / vWIZ-COVERAGE

vWIZ-Coverage

Coverage analysis and closure  ·  part of the WIOWIZ verification flow
Note: in-house EDA, not commercial grade. Built to autonomize the chip design flow.

Every coverage type, one closure picture

vWIZ-Coverage brings code, functional, assertion and formal coverage into a single dashboard, merges results across a full regression, and ranks the holes that matter, so teams reach closure faster and enter sign-off with evidence rather than assumptions.

vWIZ-Coverage on the mini-SoC example
vWIZ-Coverage on the WIOWIZ mini-SoC example
DashboardCodeToggleFSMExpressionsCovergroupsAssertionsFormal UNR

What it covers

Code coverage

Line, toggle, FSM, branch and expression coverage with source drill-down.

Functional coverage

Covergroups, bins and cross coverage, straight to the unhit bins.

Assertions

SVA assertion status tracked alongside structural and functional coverage.

Formal UNR

Formal unreachable analysis folds into the same closure view.

Merge and trend

Merge across a regression and trend coverage release over release.

Hole ranking

Ranks the highest-value coverage holes so effort goes where it counts.

Support

StageVerification, coverage closure
Coverage typesCode (line, toggle, FSM, branch, expression), functional (covergroups, bins, cross), assertion, formal UNR
InputsCoverage databases from FSimX simulation and vWIZ-Formal
OutputsMerged coverage reports, ranked holes, closure dashboard
Design levelRTL and gate, technology independent (no PDK required)
FlowNative stage in the WIOWIZ CLI, evidence-sealed

See it run

vWIZ-Coverage tour

Coverage closure across code, functional and formal on a real design.

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