vWIZ-STA is a native, sign-off-grade static timing analyzer. It takes a gate-level netlist, Liberty libraries, SDC constraints and SPEF parasitics, builds the timing graph, and produces timing, QoR and constraint reports where every finding carries a stable violation ID and each run is saved to a persistent learning database. It reports timing plus classified evidence, and never substitutes missing data: nets without parasitics are flagged and un-analyzed dimensions are shown as n/a rather than faked.
Native parsers for gate-level Verilog, Liberty (NLDM and CCS tables), SDC constraints and SPEF parasitics.
Pin nodes with cell, net and check arcs, clock network and topological ordering built from the linked design.
Per-arc NLDM bilinear lookup, a CCS current-source path where CCS tables exist, and SPEF Elmore interconnect delay from extracted RC trees.
Level-parallel arrival and required-time propagation for setup max-delay slack, bit-identical across thread counts.
report_qor summarizes worst and total negative slack and the critical endpoints, with report_timing path detail.
check_timing flags missing create_clock, missing I/O delay and unconstrained endpoints before results are trusted.
Clock-network topology summary with generated-clock and propagation health.
Selectable none, flat OCV, or depth-aware AOCV derating on the timing paths.
Every finding carries a stable VSTA category ID from an append-only registry for tracking across runs.
A stable per-path fingerprint lets the same path be compared across runs and across ECOs.
report_rootcause decomposes failing paths into wire, logic and depth contributions with a top-causes ranking.
report_signoff scores per-dimension health across setup, hold, constraint, clock and SI, with un-run dimensions marked n/a.
Each run is saved as JSON and an append-only genome accumulates classified findings across runs.
A batch runner and a PrimeTime-style interactive Tcl command flow drive read, link, update_timing and reporting.
Nets without SPEF are counted as fallback and flagged, and blockers force readiness to zero rather than hiding gaps.
| Stage | Signoff, static timing analysis and timing sign-off |
|---|---|
| Analyses | Setup slack, WNS/TNS QoR, constraint linting, clock-network health, root-cause decomposition, sign-off readiness |
| Inputs | Gate-level Verilog netlist, Liberty libraries, SDC constraints, SPEF parasitics (SPEF optional but required for sign-off-grade interconnect) |
| Delay models | NLDM bilinear, CCS current-source, SPEF Elmore interconnect, with flat fallback when no model exists |
| Derating | None, flat OCV, or depth-aware AOCV |
| Outputs | Timing, QoR and constraint reports, classified VSTA violation IDs, path fingerprints, sign-off readiness, persistent run and genome database |
| PDK / technology | Uses Liberty timing libraries characterized for the target process (technology dependent) |
| Interfaces | Batch runner and PrimeTime-style Tcl shell (read_liberty, read_verilog, link_design, read_sdc, read_parasitics, update_timing, reporting) |
| Flow | Consumes the APARA implementation handoff; downstream stage in the WIOWIZ signoff flow |
