vWIZ-Signoff is the WIOWIZ physical-verification suite. Its engines cover parasitic extraction (PEX), design-rule checking (DRC), layout-versus-schematic comparison (LVS) and layout I/O, working from hierarchical GDS to answer which conductors are connected, what resistance and capacitance they add, whether geometry violates process rules, and whether the layout implements the intended circuit.
Rule-based ground, coupling and via/segment RC extraction from hierarchical GDS, with a cell-aware mode for SoC-scale runs.
SPEF-oriented output on IEEE 1481 foundations, connectivity JSON and per-cell RC database and storage APIs.
Minimum width, spacing and area checks with Magic-deck parsing, per-rule correlation on routed digital layouts.
SPICE and gate-level Verilog input, cell fingerprints, device matching, net correspondence and open/short/parameter reporting.
Same-layer and via-based connectivity tracing with boundary-port and pin-binding derivation and power-fragment blocking.
Deterministic GDS/OASIS read, write, diff and XOR, plus cross-tile DSU merging with 128-bit boundary signatures.
| Stage | Physical verification and sign-off |
|---|---|
| Engines | PEX (wzpex), DRC (wzdrc), LVS (wzlvs) and layout I/O (vwiz-gds) |
| Extraction | Rule-based ground and coupling capacitance, segment and via resistance, single-corner, cell-aware mode for scale |
| DRC rules | Minimum width, spacing and area categories with Magic-deck parsing |
| LVS inputs | Connectivity JSON, SPICE/CDL netlists and gate-level Verilog schematic |
| Inputs | Hierarchical GDS/OASIS, LEF/DEF subset and technology files |
| Outputs | SPEF-oriented RC, connectivity JSON, DRC and LVS reports (JSON and Netgen-style text) |
| PDK / technology | PDK-dependent: DRC and LVS runsets and extraction decks are provided per foundry PDK |
| Qualification | Qualification assets for Nangate45, Sky130, ASAP7, GF180 and IHP SG13G2, with independent GDS-read correlation |
| Flow | Native stage in the WIOWIZ CLI, C++17 core with Python driver, evidence-sealed |
