vWIZ-DFT is a native design-for-test suite that carries a design from scan insertion through ATPG, BIST and JTAG to tapeout closure. Every generated pattern set is replayed through fault simulation as a consistency check, and every fault written off as redundant is backed by a DRAT-verified proof, so coverage is reported against a declared fault universe rather than asserted.
DFF-to-scan-DFF conversion, chain balancing and stitching, with scan design-rule checking on the netlist.
Stuck-at, transition (LOS/LOC), cell-aware, bridge, SDD and IDDQ pattern generation, including SAT-based ATPG.
Generated patterns are replayed through a bit-parallel fault-simulation kernel as a consistency check on detection.
Any fault written off as redundant carries a DRAT-verified proof, independently re-checked at closure.
Logic BIST with PRPG/MISR signature generation and memory BIST with SRAM inventory and March algorithms.
IEEE 1500 core wrapper and IEEE 1687 IJTAG network construction for test-access infrastructure.
Coverage is reported against a declared fault-universe denominator and is rejected unless a full-chip fault-simulation replay consistency check backs it. Policy-driven gates and decision-tree closure verdicts produce a tapeout manifest of SHA-256-stamped deliverables — patterns, STIL, reports and tester pin map.
| Stage | Design-for-test, tapeout closure |
|---|---|
| Test structures | Scan chains, LBIST/MBIST, IEEE 1500 wrapper, IEEE 1687 IJTAG |
| Fault models | Stuck-at, transition (LOS/LOC), cell-aware, bridge, SDD, IDDQ |
| Proof | Fault-sim replay consistency check, DRAT-verified redundancy proofs |
| Outputs | Patterns, STIL, coverage reports, tapeout manifest with SHA-256-stamped deliverables |
| Design level | Gate level, standard-cell / scan-library dependent |
